1. Field of the Invention
The present invention relates generally to a multiplexer circuit, and, more particularly, to a multiplexer circuit that enables a reduction in the number of devices using negative differential resistance devices, and that enables low power operation using RZ-mode signals.
2. Description of the Related Art
Currently, with the increase in the demand for broadband communication service and very high-speed Internet, very high-speed communication networks, which can transfer a large amount of information, such as images as well as voice signals, in a short time, have become required. In order to implement such very high-speed broadband systems, the development of very high-speed digital circuits is essential.
Up to now, in very high-speed digital circuits, very high-speed digital logic gates have been implemented using Heterojunction Bipolar Transistors (HBTs) or High Electron Mobility Transistors (HEMTs), which are Gallium Arsenide (GaAs) or Indium Phosphide (InP)-based very high-speed devices, in an Emitter Coupled Logic (ECL), Current Mode Logic (CML), or Source Coupled FET Logic (SCFL) circuit configuration.
Patents have been applied for or granted with respect to various conventional technologies related to multiplexers used in very high-speed digital circuits, including Korean Unexamined Patent Publication No. 10-2004-0031532, entitled “Glitch-free Asynchronous Digital Multiplexer having Power Saving Mode”.
The asynchronous digital multiplexer includes an edge detection circuit for receiving a data selection signal, detecting edges, and generating a first control signal, a selection synchronization circuit for receiving the data selection signal, a first clock input signal, and a second clock input signal, and selecting one from among the first clock input signal and the second clock input signal under the control of a second control signal, a clock signal synchronization circuit for receiving the first control signal and an output signal of the selection synchronization circuit, synchronizing the data selection signal with the selected clock input signal, and generating a second control signal, and a saving mode selection unit for receiving the second control signal, the output signal of the selection synchronization circuit and a power-down signal, and generating an output clock signal.
However, since the above-described technology uses a feedback loop, there are problems in that the construction of the circuit is complicated, so that the operating speed of the circuit is limited and power consumption increases.
That is, conventionally, when a multiplexer circuit is implemented, the multiplexer circuit is configured using four latch circuits for latching low frequency band signals, and a selection unit for multiplexing two low frequency band signals, as shown in FIG. 1.
As shown in FIG. 2, the latch circuits are configured using master-slave latch circuits. Since the latch circuit is configured using data input transistors 101 and 102, clock (CLK) input transistors 105 and 106, a current source 119, and load resistors 109 and 110, the voltage source 120 of the latch circuit should maintain a value ranging from −3.5 V to −5.5 V. Therefore, there is a problem in that the power consumption of the latch circuit increases. Further, the impedance at the output terminal increases due to the feedback transistors 103 and 104 used to latch signals, and thus there is a limitation in operating speed.
Further, FIG. 3 shows a selection unit that operates in a master-slave multiplexer in Non-Return-to-Zero (NRZ) mode. Here, when the latch circuit shown in FIG. 1 receives two low frequency signals D1 and D2 and a clock signal CLK is at a high level, a CLK transistor 205 is turned on and transmits the data input D2 to an output terminal. In contrast, when the clock signal CLK is at a low level, a CLK transistor 206 is turned on and transmits the data input D2 to the output terminal. However, since the selection unit, shown in FIG. 3, which operates in NRZ-mode, is configured such that load resistor terminals 209 and 210, data input transistor terminals 201, 202, 203, and 204, CLK input terminals 205 and 206, and a current source terminal 219 are connected in series to one another, there is a problem in that power consumption is high.